kd's homebrew archive // 450 GiB free of 1.78 TiB

c File Name Size Date
parent folder--
-Advanced Memory Interfaces [VdPXjZB1VCM].mkv1594460462025-09-16 18:40:06
-Airthmetic Logic Unit (ALU) [_xsEVXv6zrg].mkv1768292132025-09-16 18:40:23
-Basic Control [TgwMKweerKo].mkv1219267872025-09-16 18:40:48
-Building Complex Circuit [Eq-Iy7F-dX4].mkv953478392025-09-16 18:35:51
-Bus Interface Design [6MGvtKMDi6A].mkv705338882025-09-16 18:41:16
-CPU [hJnXcjxbgTk].mkv1360272292025-09-16 18:41:22
-CPU-Pipeline [SEiFp0n9zK4].mkv800350592025-09-16 18:41:48
-Coding for Synthesis [puyALBWaHtQ].mkv1172607122025-09-16 18:37:20
-Control and Datapath [d7UjZXXSoWU].mkv1106749362025-09-16 18:39:14
-Custom 16 bit ISA [u5g9Y9Clc14].mkv1761444932025-09-16 18:41:01
-Delay Models [jmzQMZT5njs].mkv615951832025-09-16 18:36:01
-Design Process [q6i26dyyXew].mkv1659095602025-09-16 18:35:15
-Design and Test [S01R7n7YBrg].mkv840660642025-09-16 18:39:57
-Designing Parameterized FSMs [QtFwq_ZVnq0].mkv1237722242025-09-16 18:38:10
-Electronic Design Automation [63Y3DW2CaPw].mkv1096334622025-09-16 18:35:29
-FPGA Memory [xL_Uu7ZbqF4].mkv1466679032025-09-16 18:40:31
-FPGA SoC Architectures [TI2BQdFpzcE].mkv834332172025-09-16 18:42:09
-FSM Modeling in Verilog [Na5cBsjk_-Q].mkv1378058322025-09-16 18:38:01
-Field Programming Gated Array [BG26vmsy1OU].mkv1519917022025-09-16 18:35:34
-Flip-Flops and Register [-9oOYQ5z-RE].mkv1603458932025-09-16 18:37:05
-From Mathematics to Digital Hardware [41qh76WcwJE].mkv1105464602025-09-16 18:40:17
-Hardware Description Language [8ePBc6NE1q4].mkv2537156522025-09-16 18:35:20
-Hierarchical Design [OLVGTaOLLSk].mkv2271861352025-09-16 18:35:19
-Hierarchical Design [qIHQ_DOFZZY].mkv1040922852025-09-16 18:38:50
-Immediate Operands [hio_zitISLc].mkv751025142025-09-16 18:40:43
-Instruction Encoding [6leur9op6_Q].mkv1297860402025-09-16 18:40:25
-Integration- Components to Systems [9WuPZ7e2y18].mkv439874322025-09-16 18:40:58
-Introduction to Digital System [TiAB8RZIdlk].mkv2145799892025-09-16 18:35:17
-Introduction to Finite State Machines (FSMs) [CT0idY8mI0Y].mkv2377364262025-09-16 18:37:45
-Logic Modelling using verilog [ToJXfXxJrlE].mkv1520915972025-09-16 18:36:34
-Memory Mapping [Ipol26Yta9k].mkv1436521512025-09-16 18:41:46
-Memory [vLoXldf5RfY].mkv1162829412025-09-16 18:40:45
-Mnemonics and Instructions [N_aJ9RKwebs].mkv852944532025-09-16 18:41:02
-More on Testbenches [BMirn3DAUoI].mkv1115641282025-09-16 18:35:52
-Multi Objective Optimization [HMP8EK4QVbM].mkv1456331042025-09-16 18:39:35
-Parallel Execution [Eg8iuADZCMo].mkv705216872025-09-16 18:42:02
-Parallel Multiplier [m9UNPyGbeyI].mkv1884082942025-09-16 18:39:16
-Performance Optimizaton [HzbEZgueEEw].mkv2387660452025-09-16 18:42:50
-Program Flow Control [9rSJL_doVe8].mkv994065882025-09-16 18:40:47
-Register File [poPNsOKUWKU].mkv959944672025-09-16 18:40:11
-Registers and Memory [Hp0YP3Ry49E].mkv1892329462025-09-16 18:39:50
-Registers to RAM [85Qa-YwQEc8].mkv2520292172025-09-16 18:40:01
-Sequential Logic Modeling [P8DA_oPJZ9c].mkv1037976522025-09-16 18:36:21
-Sequential Test Benches [_fe9Rh6g8kY].mkv416606192025-09-16 18:36:57
-Simulation Time and Delays [YbwTt3Yqaos].mkv809062472025-09-16 18:35:41
-SoC： Architecture Fundamentals [y4bEOS9viu8].mkv1653870902025-09-16 18:41:19
-SoC： Design Challenges [XOftXc7dIcU].mkv1480977342025-09-16 18:41:33
-SoC： Hardware ⧸ Software Interfaces [A3OC4p-xn9Y].mkv1061886112025-09-16 18:41:31
-SoC： IP integration [tkJD9RTwvi8].mkv823267382025-09-16 18:41:16
-SoC： On-Chip Communication [exp71ZWfeek].mkv1557573802025-09-16 18:41:45
-Synthesis (Part-2) [HX_tx_expvQ].mkv1879457822025-09-16 18:39:38
-Synthesis [UZrvekwrHX8].mkv1734551132025-09-16 18:39:39
-Synthesis and RTL [Uihw2yaYmAk].mkv629581362025-09-16 18:36:33
-Testbench Development for Traffic Light Controller [aXRerYp6Y9k].mkv1788347022025-09-16 18:38:37
-Testbench [oLKUe7lAnHE].mkv971566732025-09-16 18:35:38
-The Journey Forward [yFPxLKV3pM8].mkv651467722025-09-16 18:42:20
-Timing [EeuL_uiLXMg].mkv1863616192025-09-16 18:37:57
-Traffic Light Control System Overview [5araO8J1fCo].mkv1328386262025-09-16 18:38:42
-Verification Strategy [Pm6Gfsk-7Y4].mkv396587422025-09-16 18:39:14
-Verification and Validation [UVlflFoDS4U].mkv1060381612025-09-16 18:42:07
-Verilog Design for Traffic Light Controller [g8heIE6nM58].mkv2092993412025-09-16 18:39:34
-Verilog Simulators [I6_Up6lstBU].mkv650214812025-09-16 18:36:10

control-panel