kd's homebrew archive // 450 GiB free of 1.78 TiB

c File Name Size Date
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-W10_L1_S-R Latch [mUlYO2fEImY].mkv1586848052025-09-16 18:12:03
-W10_L2_Clocked S-R Latch [urj5KreTFGw].mkv1072240692025-09-16 18:12:43
-W10_L3_T-Flip Flop [9vpJynRw-14].mkv1519808082025-09-16 18:12:09
-W10_L4_JK-Flip Flop [E95xZAUXi7I].mkv1568580802025-09-16 18:12:17
-W10_L5_Registers [jo11IgnALNM].mkv1855797942025-09-16 18:12:32
-W10_L6_Shift Registers [Rq80lLYbqa0].mkv2285754662025-09-16 18:12:36
-W10_L7_Scan Chain [HH-I6HTXgnY].mkv1287263592025-09-16 18:14:23
-W11_L1_Introduction to Finite State Machine (FSM) [rs5paGlPs90].mkv994001832025-09-16 18:12:46
-W11_L2_Analysis of D-FlipFlop based FSMs [HZSHFKuoZ4w].mkv2243240822025-09-16 18:13:21
-W11_L3_Analysis of JK-FlipFlop based FSMs [ELSLqZiOgh8].mkv1805438732025-09-16 18:13:24
-W11_L4_Analysis of T-FlipFlop based FSMs [rF4Wc5PStIk].mkv1712814682025-09-16 18:13:24
-W11_L5_Designing sequence detector using D-FlipFlops [ugAeWbcKFaQ].mkv2305236322025-09-16 18:14:34
-W11_L6_Designing sequence detector using JK-FlipFlops [4_GiR4KZL74].mkv1073219652025-09-16 18:13:41
-W12_L10_Application of Digital System- Hamming Code-Part-1 [TRboQtYgLVc].mkv4024816762025-09-16 18:15:45
-W12_L11_Application of Digital System- Hamming Code - Part - 2 [WEXr6PI3Jfc].mkv3595338932025-09-16 18:16:41
-W12_L1_Designing 3-bit Counter using D-FlipFlops [L-O1dTQsdz8].mkv1353451232025-09-16 18:14:00
-W12_L2_Designing Counters using Full Adders [OA-K1VEBWXw].mkv2271989352025-09-16 18:14:18
-W12_L3_Counters with parallel load [VmAsKqT5GVE].mkv782522442025-09-16 18:14:19
-W12_L4_Pipelining [voKdyRPiBZk].mkv2623857242025-09-16 18:14:38
-W12_L5_Maximum operating frequency of pipelined circuits [uNSnSpBSG1o].mkv2622705802025-09-16 18:15:13
-W12_L6_Designing Non overlapping clock generator [LCUAinWxI6A].mkv1194488322025-09-16 18:14:54
-W12_L7_Cirtical path analysis [AxFLVOBLyc0].mkv1736395682025-09-16 18:15:27
-W12_L8_Asynchronous sequential circuits [4yupVArzdOk].mkv2226019952025-09-16 18:15:35
-W12_L9_Application of Digital System Error Correction [XSFvmvsB5G4].mkv3571145852025-09-16 18:15:43
-W1_L1_Introduction [1oHz2svCOC8].mkv2228703362025-09-16 18:04:56
-W1_L2_Course Structure [eoeFSeWK4lg].mkv1574590202025-09-16 18:04:53
-W1_L3_Digital Compute and logic representation [YRMkmNwN4MY].mkv1873997692025-09-16 18:04:55
-W1_L4_Experiment Voltage Transfer Characteristics [WovYj666lWM].mkv1716302832025-09-16 18:04:55
-W1_L5_Small Signal Analysis [d95KQz19NQE].mkv1378781332025-09-16 18:05:07
-W1_L6_Theory： Voltage Transfer Characteristics [7sZ4fCUEHt0].mkv1864827402025-09-16 18:05:13
-W1_L7_Noise Margin [7mb2WrcfAio].mkv1245746412025-09-16 18:05:10
-W2_L1_Binary Number system [x7QuQ7XLO4Q].mkv1682050962025-09-16 18:05:31
-W2_L2_Binary representation of decimal numbers [4Q6v0AOz6-0].mkv1902253992025-09-16 18:05:23
-W2_L3_Hexadecimal & Octal representation of decimal numbers [TcLScmCH2DY].mkv1749836122025-09-16 18:05:27
-W2_L4_Relation between Binary and Hexadecimal representation [dXvH0XJ908I].mkv1079929392025-09-16 18:05:26
-W2_L5_Relation between Binary and Octal representation [HhkyIzgjgKQ].mkv632847062025-09-16 18:05:37
-W2_L6_Relation between Hexadecimal and Octal representation [FbD9BetK-6Q].mkv851953712025-09-16 18:05:40
-W2_L7_Signed Magnitude representation [bnV8bqOCmMk].mkv1259544992025-09-16 18:05:41
-W2_L8_2’s complement representation intuition [JrzLLRKZ2ZA].mkv2209439382025-09-16 18:05:48
-W2_L9_Ranges of the Signed Magnitude & 2’s complement representation [926oWgT8UqA].mkv1299571572025-09-16 18:05:51
-W3_L1_Sign Extension for unsigned and signed number [e3oalE7Jy4g].mkv1480391522025-09-16 18:06:02
-W3_L2_.Sign Extension for 2’s complement representation [4uiSnXl1X9M].mkv1322637172025-09-16 18:06:51
-W3_L3_Negative of a number using 2’s complement [JJGbSxqJG7Y].mkv764132142025-09-16 18:06:00
-W3_L4_Logic Gates： AND, OR [Vj0-w4Qdncc].mkv2013460252025-09-16 18:07:31
-W3_L5_Logic Gates： XOR, NAND, NOR, XNOR [lKaSkILLn98].mkv1806458602025-09-16 18:06:19
-W3_L6_Truth table for basic gates [HoblrfPGccE].mkv1775460422025-09-16 18:06:23
-W3_L7_Truth table for large input circuits [v_4M-q2roaM].mkv1323556652025-09-16 18:06:35
-W3_L8_Introduction to Boolean Algebra [FoQ3efF1S7Y].mkv944216762025-09-16 18:06:37
-W4_L1_Properties in Boolean Algebra [jX8BH0LgvKY].mkv1875296862025-09-16 18:06:52
-W4_L2_De-Morgan's Laws [wc0B-ZG8X-8].mkv2005073902025-09-16 18:06:53
-W4_L3_Boolean simplification [mCUu5tzSZOo].mkv2275499612025-09-16 18:07:10
-W4_L4_Canonical Sum of Products representation [FfffGscd-Hk].mkv1334822402025-09-16 18:07:10
-W4_L5_Implementing Boolean function with minimum gates [sHuRr_hmZVQ].mkv2231224042025-09-16 18:07:38
-W4_L6_Minterm representation of Boolean expressions [vK1-kEmKXc8].mkv881355292025-09-16 18:07:37
-W4_L7_Canonical Products of Sum representation [hYDQwvdUImg].mkv1008973162025-09-16 18:07:24
-W4_L8_ Maxterm representation of Boolean expressions [_w_Zi9IrS2w].mkv551022852025-09-16 18:07:37
-W5_L1_Boolean Simplification using Karnaugh Map [kiNRhbcRWiQ].mkv1653901192025-09-16 18:08:10
-W5_L2_3-Variable K Map [IeEXmextYNk].mkv2111660562025-09-16 18:07:57
-W5_L3_4-Variable K Map [hSUu_CyalO8].mkv1641354772025-09-16 18:10:46
-W5_L4_K- Map with don't care condition [P14TO53PfbQ].mkv1531933542025-09-16 18:08:07
-W5_L5_Designing logic circuits using K Maps [5MUyn7sUMIU].mkv1928670682025-09-16 18:08:15
-W6_L1_Implementing Boolean expression using AND,OR,NOT gates [3zYGebIv5gI].mkv1388809612025-09-16 18:08:23
-W6_L2_Universal Gates [u4dfI3zysWo].mkv1428788912025-09-16 18:08:38
-W6_L3_Implementing XOR gate using NAND gates [3UN89Xa06lQ].mkv876534892025-09-16 18:08:27
-W6_L4_Decoders [vqhENfEq6DY].mkv1305576202025-09-16 18:08:36
-W6_L5_Multiplexers [f81tL6Dk26E].mkv790502872025-09-16 18:09:06
-W6_L5_Multiplexers [f9XVbYgnP-4].mkv749036342025-09-16 18:08:42
-W6_L6_Tristate Inverter [hMhRG1Ouhpc].mkv1618060532025-09-16 18:09:12
-W6_L7_Delay of logic gates [k-lWBWm0j5I].mkv1009453372025-09-16 18:08:52
-W6_L8_Static Timing Analysis [2eDDUoIxJeM].mkv1256543562025-09-16 18:08:56
-W7_L1_2_4 Decoder using 3_8 Decoder [lV2BMK_P8jA].mkv1317796482025-09-16 18:09:10
-W7_L2_6_64 Decoder using 3_8 Decoders [igl-_G1X3lE].mkv2904275252025-09-16 18:10:17
-W7_L3_7_128 Decoder using 3_8 Decoders [ZSuqciaO084].mkv1867392602025-09-16 18:09:28
-W7_L4_Implementing multiplexers using decoders [mjJLdqCC4RA].mkv2210377312025-09-16 18:09:35
-W7_L5_Higher order Mux using lower order Mux [lz0o1KyqcME].mkv1813489632025-09-16 18:10:22
-W7_L6_Encoders [j-v3diwMCKE].mkv1799375992025-09-16 18:10:18
-W7_L7_Priority Encoder [fgyScp4FDlc].mkv983117492025-09-16 18:10:34
-W8_L1_Implementing Boolean function using Decoders [AFy9wnZfqlU].mkv1472405442025-09-16 18:10:35
-W8_L2_Implementing Boolean function using Multiplexers [c-1Zk0SLO9c].mkv1718811372025-09-16 18:11:06
-W8_L3_Implementing Boolean function using Look Up Table [h3E0vtbGgBE].mkv812530352025-09-16 18:10:47
-W8_L4_Unsigned and Signed Binary Addition [RM6CvMOkUv8].mkv2097786272025-09-16 18:11:08
-W8_L5_Ripple Carry Adder [ptTElREfZSw].mkv1950301222025-09-16 18:11:04
-W8_L6_Magnitude Comparator [K7tkady8pQg].mkv1951144112025-09-16 18:11:08
-W8_L7_Binary Coded Decimal to Binary conversion [Y_ttQdAEV6w].mkv1301063482025-09-16 18:11:41
-W9_L1_Introduction to Sequential circuits [oU-AOBsdftA].mkv1092300682025-09-16 18:11:26
-W9_L2_Designing a counter using Ripple Carry Adder [vTVCf6apCMg].mkv1926392542025-09-16 18:12:18
-W9_L3_D-Flip Flop [_L-jI9W5hwM].mkv904948722025-09-16 18:11:24
-W9_L4_D-Latch [VgPXXrh1P48].mkv829979182025-09-16 18:11:31
-W9_L5_Master Slave D-Flip Flop [TYosQVd37jw].mkv1305238342025-09-16 18:11:52
-W9_L6_Tri-state Inverter based D-Latch [mJIyem9QT90].mkv1611365582025-09-16 18:11:43
-W9_L7_Tri-state Inverter based Master Slave D-Flip Flop [hmPXCUV-8-o].mkv2056471262025-09-16 18:11:49
-W9_L8_Function Table of D-Latch [wCX8RKTqzZ8].mkv596066812025-09-16 18:11:55

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